An SOI (Silicon On Insulator) substrate has been used for lower power consumption in an LSI. Recently, higher density or integration of semiconductor transistors has been required for an LSI. Transistors may be isolated by LOCOS (Local Oxidation of Silicon) regions, which are formed by oxidizing selectively an SOI layer.
FIG. 1 is a cross sectional view illustrating a conventional LOCOS region of a semiconductor device. As shown in FIG. 1, an insulating layer 13 is formed on a substrate. A channel-region of an SOI layer 10 is formed on the insulating layer 13. The two adjacent channel regions are isolated by a LOCOS region 12 from each other. A gate oxide layer 15 is formed on an each channel region. A gate layer 11 is formed on the gate oxide layer 15 and on the LOCOS regions 12.
The channel region (10) has a sharply shaped ends, called bird's beak. The bird's beak generates parasitic channel regions 14, which allows an electric current flow with a voltage that is lower than the gate voltage (threshold voltage). This phenomenon is called “hump”. In order to avoid or reduce such a hump phenomenon, impurities may be implanted in the parasitic channel regions 14. Usually, impurities are implanted a boundary between the LOCOS region 12 and the SOI layer 10. If the amount of impurities is not sufficient, it would be difficult to avoid or reduce a hump phenomenon efficiently.
According to the conventional method related to FIG. 1, impurities are implanted into the bird's beak of the LOCOS region 12 entirely. Impurities are implanted into the boundary between the LOCOS region 12 and the SOI layer 10 in a vertical direction. In other words, the impurities are implanted in an inclined direction, for example, forty-five degrees from the horizontal direction. In this case, it would be difficult that the LOCOS regions 12 are formed accurately in location due to a shadowing phenomenon. As a result, the conventional technology is not appropriate to a higher integration of semiconductor device, having a narrow gate width.
Another way of suppressing a hump phenomenon is described in Japanese Patent Publication Kohkai H10-93101. According to the publication, as shown in FIG. 2, an insulating layer 23 is formed on a semiconductor substrate 26. A channel region (p-type semiconductor layer) 20 is formed on the insulating layer 23. The channel region 20 is isolated from adjacent channel regions (not shown) by an isolation layer 22. A gate insulation layer 25 is formed on the channel region 20. A gate material 21 is formed on the isolation layer 22 and the gate insulation layer 25. The isolation layer 22 is formed from BSG (Boron-doped Silicate Glass) film. When a thermal treatment is carried out, p-type impurities are diffused from the isolation layer 22 into a diffusion region 24, so that a high-impurity diffusion region 24 is formed on a side surface of the channel region 20.
Since, a p-type impurities are implanted into the diffusion regions 24, a BSG film, which is a supply source of high-density impurities to the diffusion regions 24, is used as a buried oxide layer to avoid a hump phenomenon of PMOS transistor. If a hump is generated on a PMOS transistor, such a hump could not be avoided by the BSG film.
Still another conventional way to inhibit a parasitic transistor, a nitride layer, which is used as a mask when forming LOCOS regions, is selectively etched with a high-temperature phosphoric acid. By such an etching process, the nitride layer is partially removed in a horizontal direction, so that the LOCOS regions are exposed partially. After that, impurities are implanted into ends of the exposed LOCOS regions in a vertical direction of the substrate. The implanted impurities restrain generation of a parasitic transistor. However, it is difficult to control removing amount of the nitride layer, since the nitride layer is removed in a wet-etching process. As a result, it is difficult to apply the above described conventional technology to a semiconductor device having a narrow channel region and gate width.